BZHI: Zero High Bits From Index

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Opcode and MnemonicEncoding16 bit Mode32 bit Mode64 bit ModeCPUID Feature FlagDescription
VEX.LZ.0F38.W0 F5 /r
BZHI r32a, r/m32, r32b
VEXInvalidValidValidBMI2Zeros the bits in r/m32 starting from the bit index specified in r32b. Stores the result in r32a.
VEX.LZ.0F38.W1 F5 /r
BZHI r64a, r/m64, r64b
VEXInvalidInvalidValidBMI2Zeros the bits in r/m64 starting from the bit index specified in r64b. Stores the result in r64a.

Encoding

EncodingOperand 1Operand 2Operand 3
VEXModRM.reg[w]ModRM.r/m[r]VEX.vvvv[r]

Description

The BZHI instruction zeros the high bits of the first source operand starting at the index specified in the lowest 8 bits of the second source operand. The result is stored in the destination operand.

The low 8 bits of the second source operand (the index) must not exceed the bit width of the operands. In other words, for the 32 bit form, the second source operand's low 8 bits must be 31 or less. The 64 bit form changes this requirement to 63 or less.

The operand size (W bit) is always 32 bits if not in Long Mode. In other words, in Protected and Compatibility Mode, VEX.W1 is treated as VEX.W0.

The length field (L bit) must be zero (signifying 128 bit vectors). Attempts to execute with VEX.L1 (256 bit vectors) will cause a #UD exception.

Operation

This pseudo-code uses C# syntax. A list of the types used is available here.
public void BZHI_32(ref uint dest, uint src, uint idx)
{
  uint n = idx.Bit[0..8];
  if (n < 32)
  {
    dest[n..32] = 0;
    CF = 0;
  }
  else
  {
    CF = 1;
  }
}

public void BZHI_64(ref uint dest, uint src, uint idx)
{
  uint n = idx.Bit[0..8];
  if (n < 64)
  {
    dest[n..64] = 0;
    CF = 0;
  }
  else
  {
    CF = 1;
  }
}

Flags Affected

CF (carry flag)
Set if the index is too large. Cleared otherwise.
PF (parity flag)
Undefined.
AF (auxiliary flag)
Undefined.
ZF (zero flag)
Set according to the result.
SF (sign flag)
Set according to the result.
OF (overflow flag)
Cleared.

C Intrinsics

Exceptions

SIMD Floating-Point

None

Other

See Exceptions Type 13.

Manual Changes

This is a list of changes that have been made from the Intel® 64 and IA-32 Architectures Software Developer’s Manual. These changes were against version 73 (dated ).

  • The BZHI r64a, r/m64, r64b form is incorrectly documented as being "not encodable" in 32 bit mode. This is misleading as it is encodable, but is defined to be treated as the 32 bit form.