BTC: Bit Test and Complement

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Opcode and MnemonicEncoding16 bit Mode32 bit Mode64 bit ModeDescription
0F BB /r
BTC r/m16, r16
MRValidValidValidStore the bit specified in r16 from r/m16 into the CF flag before complementing (inverting) the selected bit.
0F BB /r
BTC r/m32, r32
MRValidValidValidStore the bit specified in r32 from r/m32 into the CF flag before complementing (inverting) the selected bit.
REX.W 0F BB /r
BTC r/m64, r64
MRNot EncodableNot EncodableValidStore the bit specified in r64 from r/m64 into the CF flag before complementing (inverting) the selected bit.
0F BA /7 ib
BTC r/m16, imm8
MIValidValidValidStore the bit specified in imm8 from r/m16 into the CF flag before complementing (inverting) the selected bit.
0F BA /7 ib
BTC r/m32, imm8
MIValidValidValidStore the bit specified in imm8 from r/m32 into the CF flag before complementing (inverting) the selected bit.
REX.W 0F BA /7 ib
BTC r/m64, imm8
MINot EncodableNot EncodableValidStore the bit specified in imm8 from r/m64 into the CF flag before complementing (inverting) the selected bit.

Encoding

EncodingOperand 1Operand 2
MRModRM.r/m[rw]ModRM.reg[r]
MIModRM.r/m[rw]imm8[r]

Description

The BTC instruction selects a bit from the destination operand and stores it in the CF flag. The specific bit selected is specified in the source operand. Afterwards, the selected bit is complemented (inverted) and saved in the destination operand.

If the source operand references a bit higher than the width of the destination operand (eg. the 21st bit in a 16 bit register), the upper bits are ignored. In other words, attempting to reference the 21st bit of a 16 bit register only accesses the \i5th} bit (as 21 modulo 16 is 5).

Operation

This pseudo-code uses C# syntax. A list of the types used is available here.
public void BTC_16(ushort src, ushort idx)
{
  CF = src.Bit[idx % 16];
  src.Bit[idx % 16] = ~CF;
}

public void BTC_32(uint src, uint idx)
{
  CF = src.Bit[idx % 32];
  src.Bit[idx % 32] = ~CF;
}

public void BTC_64(ulong src, ulong idx)
{
  CF = src.Bit[idx % 64];
  src.Bit[idx % 64] = ~CF;
}

Flags Affected

CF (carry flag)
Set if the selected bit is set (before being complemented). Cleared otherwise.
PF (parity flag)
Undefined.
AF (auxiliary flag)
Undefined.
ZF (zero flag)
Unmodified.
SF (sign flag)
Undefined.
OF (overflow flag)
Undefined.

Exceptions

Protected Mode

#UD
If the LOCK prefix is used, but the destination is not a memory operand.
#GP(0)
If the memory operand's effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS segment register contains a NULL segment selector.
#SS(0)
If a memory operand's effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.

Real-Address Mode

#UD
If the LOCK prefix is used, but the destination is not a memory operand.
#GP
If the memory operand's effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand's effective address is outside the SS segment limit.

Virtual-8086 Mode

#UD
If the LOCK prefix is used, but the destination is not a memory operand.
#GP(0)
If the memory operand's effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)
If a memory operand's effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.

Compatibility Mode

Same exceptions as protected mode.

Long Mode

#UD
If the LOCK prefix is used, but the destination is not a memory operand.
#GP(0)
If the memory address is in a non-canonical form.
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.