BLSI: Extract Lowest Set Bit

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Opcode and MnemonicEncoding16 bit Mode32 bit Mode64 bit ModeCPUID Feature FlagDescription
VEX.LZ.0F38.W0 F3 /3
BLSI r32, r/m32
VEXInvalidValidValidBMI1Extracts the lowest set bit from r/m32, and sets that same bit in r32. All other bits in r32 are cleared.
VEX.LZ.0F38.W1 F3 /3
BLSI r64, r/m64
VEXInvalidValidInvalidBMI1Extracts the lowest set bit from r/m64, and sets that same bit in r64. All other bits in r64 are cleared.


EncodingOperand 1Operand 2


The BLSI instruction extracts the lowest set bit in the source operand and sets that same bit in the destination operand. All other bits in the destination operand are zeroed.

The CF flag is set if the source is not zero. This can be useful to detect if the destination operand will have anything set without actually testing it.

The operand size (W bit) is always 32 bits if not in Long Mode. In other words, in Protected and Compatibility Mode, VEX.W1 is treated as VEX.W0.

The length field (L bit) must be zero (signifying 128 bit vectors). Attempts to execute with VEX.L1 (256 bit vectors) will cause a #UD exception.


This pseudo-code uses C# syntax. A list of the types used is available here.
public void BLSI_32(ref uint dest, uint src)
  dest = (-src) & src;
  CF = (src != 0);

public void BLSI_64(ref ulong dest, ulong src)
  dest = (-src) & src;
  CF = (src != 0);

Flags Affected

CF (carry flag)
Set if the source is not zero. Cleared otherwise.
PF (parity flag)
AF (auxiliary flag)
ZF (zero flag)
Set according to the result.
SF (sign flag)
Set according to the result.
OF (overflow flag)

C Intrinsics


SIMD Floating-Point



See Exceptions Type 13.

Manual Changes

This is a list of changes that have been made from the Intel® 64 and IA-32 Architectures Software Developer’s Manual. These changes were against version 73 (dated ).

  • The BLSI r64, r/m64 form is incorrectly documented as being "not encodable" in 32 bit mode. This is misleading as it is encodable, but is defined to be treated as the 32 bit form.