BEXTR: Bit Extract Field

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Opcode and MnemonicEncoding16 bit Mode32 bit Mode64 bit ModeCPUID Feature FlagDescription
VEX.LZ.0F38.W0 F7 /r
BEXTR r32a, r/m32, r32b
RMVInvalidValidValidBMI1Contiguous bitwise extraction from r/m32 using r32b as a control. Stores the result in r32a.
VEX.LZ.0F38.W1 F7 /r
BEXTR r64a, r/m64, r64b
RMVInvalidInvalidValidBMI1Contiguous bitwise extraction from r/m64 using r64b as a control. Stores the result in r64a.


EncodingOperand 1Operand 2Operand 3


The BEXTR instruction extracts contiguous bits from the first source operand using using index and length values provided in the second source operand. The result is stored in the destination operand.

The control register contains 16 bits: the lower eight are the starting index into the slice, and the upper eight is the amount of bits to extract. In other words, the destination register will be filled least significant to most significant by copying from the source, beginning at the starting position (where 0 indicates the least significant bit). The length field determines how many bits are extracted. This operation can be thought of as shifting the source right by "start" bits and then zeroing all bits with positions greater than or equal to "length".

The operand size (W bit) is always 32 bits if not in Long Mode. In other words, in Protected and Compatibility Mode, VEX.W1 is treated as VEX.W0.

The length field (L bit) must be zero (signifying 128 bit vectors). Attempts to execute with VEX.L1 (256 bit vectors) will cause a #UD exception.


This pseudo-code uses C# syntax. A list of the types used is available here.
public void BEXTR_32(ref uint dest, uint src1, uint src2)
  uint start = src2[0..8];
  uint len = src2[8..16];
  uint end = start + len;
  dest = src1[start..end];

public void BEXTR_64(ref ulong dest, ulong src1, ulong src2)
  ulong start = src2[0..8];
  ulong len = src2[8..16];
  ulong end = start + len;
  dest = src1[start..end]

Flags Affected

CF (carry flag)
PF (parity flag)
AF (auxiliary flag)
ZF (zero flag)
Set according to the result.
SF (sign flag)
OF (overflow flag)

C Intrinsics


SIMD Floating-Point



See Exceptions Type 13.

If VEX.L is not 0.

Manual Changes

This is a list of changes that have been made from the Intel® 64 and IA-32 Architectures Software Developer’s Manual. These changes were against version 73 (dated ).

  • The "Exceptions" section lists the #UD as occurring when VEX.W = 1. Assuming they forgot to say "when in 32 bit mode", it still wouldn't make sense as their description lists VEX.W = 1 to be treated as VEX.W = 0 in 32 bit mode. The most likely typo seems to be that it should be VEX.L.
  • The BEXTR r64a, r/m64, r64b form is incorrectly documented as being "not encodable" in 32 bit mode. This is misleading as it is encodable, but is defined to be treated as the 32 bit form.