ANDPS: Logical AND Packed Single-Precision Floating-Point Values

For information about interpreting this page, see the help page.
Opcode and MnemonicEncoding16 bit Mode32 bit Mode64 bit ModeCPUID Feature FlagDescription
NP 0F 54 /r
ANDPS xmm1, xmm2/m128
LEGACYInvalidValidValidSSE2ANDs packed single-precision floating-point values from xmm2/m128 and xmm1. Stores the result in xmm1.
VEX.128.0F.WIG 54 /r
VANDPS xmm1, xmm2, xmm3/m128
VEXInvalidValidValidAVXANDs packed single-precision floating-point values from xmm3/m128 and xmm2. Stores the result in xmm1.
VEX.256.0F.WIG 54 /r
VANDPS ymm1, ymm2, ymm3/m256
VEXInvalidValidValidAVXANDs packed single-precision floating-point values from ymm3/m256 and ymm2. Stores the result in ymm1.
EVEX.128.0F.W0 54 /r
VANDPS xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst
EVEXInvalidValidValidAVX512VL
AVS512DQ
ANDs packed single-precision floating-point values from xmm3/m128/m32bcst and xmm2. Stores the result in xmm1.
EVEX.256.0F.W0 54 /r
VANDPS ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst
EVEXInvalidValidValidAVX512VL
AVS512DQ
ANDs packed single-precision floating-point values from ymm3/m256/m32bcst and ymm2. Stores the result in ymm1.
EVEX.512.0F.W0 54 /r
VANDPS zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst
EVEXInvalidValidValidAVX512DQANDs packed single-precision floating-point values from zmm3/m512/m32bcst and zmm2. Stores the result in zmm1.

Encoding

EncodingTuple TypeOperand 1Operand 2Operand 3
LEGACYN/AModRM.reg[rw]ModRM.r/m[r]
VEXN/AModRM.reg[rw]VEX.vvvv[r]ModRM.r/m[r]
EVEXFullModRM.reg[rw]EVEX.vvvv[r]ModRM.r/m[r]

Description

The (V)ANDPS instruction ANDs four, eight, or sixteen 32 bit integer values from the first source operand to the second source operand. The result is stored in in the destination operand.

This instruction, despite being named as if it operates on floating-point numbers, internally operates on 32 bit integers. The "Operation" section below has been updated to reflect this (using SimdU32 instead of SimdF32).

All versions except the legacy SSE version zero the unused upper SIMD register bits.

Operation

This pseudo-code uses C# syntax. A list of the types used is available here.
public void ANDPS(SimdU32 dest, SimdU32 src)
{
  dest[0] &= src[0];
  dest[1] &= src[1];
  dest[2] &= src[2];
  dest[3] &= src[3];
  // dest[4..Simd.Max] (unmodified)
}

void VANDPS_Vex(SimdU32 dest, SimdU32 src1, SimdU32 src2, int kl)
{
  for (int n = 0; n < kl, n++)
    dest[n] = src1[n] & src2[n];
  dest[kl..Simd.MAX] = 0;
}
public void VANDPS_Vex128(SimdU32 dest, SimdU32 src1, SimdU32 src2)
{
  VANDPS_Vex(dest, src1, src2, 4);
}
public void VANDPS_Vex256(SimdU32 dest, SimdU32 src1, SimdU32 src2)
{
  VANDPS_Vex(dest, src1, src2, 8);
}

void VANDPS_EvexMemory(SimdU32 dest, SimdU32 src1, SimdU32 src2, KMask k, int kl)
{
  for (int n = 0; n < kl, n++)
  {
    if (k[n])
    {
      if (EVEX.b)
        dest[n] = src1[n] & src2[0];
      else
        dest[n] = src1[n] & src2[n];
    }
    else if (EVEX.z)
    {
      dest[n] = 0;
    }
  }
  dest[kl..Simd.MAX] = 0;
}
public void VANDPS_Evex128Memory(SimdU32 dest, SimdU32 src1, SimdU32 src2, KMask k)
{
  VANDPS_EvexMemory(dest, src1, src2, k, 4);
}
public void VANDPS_Evex256Memory(SimdU32 dest, SimdU32 src1, SimdU32 src2, KMask k)
{
  VANDPS_EvexMemory(dest, src1, src2, k, 8);
}
public void VANDPS_Evex512Memory(SimdU32 dest, SimdU32 src1, SimdU32 src2, KMask k)
{
  VANDPS_EvexMemory(dest, src1, src2, k, 16);
}

void VANDPS_EvexRegister(SimdU32 dest, SimdU32 src1, SimdU32 src2, KMask k, int kl)
{
  for (int n = 0; n < kl, n++)
  {
    if (k[n])
      dest[n] = src1[n] & src2[n];
    else if (EVEX.z)
      dest[n] = 0;
  }
  dest[kl..Simd.MAX] = 0;
}
public void VANDPS_Evex128Register(SimdU32 dest, SimdU32 src1, SimdU32 src2, KMask k)
{
  VANDPS_EvexRegister(dest, src1, src2, k, 4);
}
public void VANDPS_Evex256Register(SimdU32 dest, SimdU32 src1, SimdU32 src2, KMask k)
{
  VANDPS_EvexRegister(dest, src1, src2, k, 8);
}
public void VANDPS_Evex512Register(SimdU32 dest, SimdU32 src1, SimdU32 src2, KMask k)
{
  VANDPS_EvexRegister(dest, src1, src2, k, 16);
}

C Intrinsics

Exceptions

SIMD Floating-Point

None

Other

VEX encoded form: see Exceptions Type 4.

EVEX encoded form: see Exceptions Type E4.