ANDNPD: Logical AND NOT Packed Double-Precision Floating-Point Values

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Opcode and MnemonicEncoding16 bit Mode32 bit Mode64 bit ModeCPUID Feature FlagDescription
66 0F 55 /r
ANDNPD xmm1, xmm2/m128
LEGACYInvalidValidValidSSE2ANDs packed double-precision floating-point values from the inverted form of xmm2/m128 and xmm1. Stores the result in xmm1.
VEX.128.66.0F.WIG 55 /r
VANDNPD xmm1, xmm2, xmm3/m128
VEXInvalidValidValidAVXANDs packed double-precision floating-point values from the inverted form of xmm3/m128 and xmm2. Stores the result in xmm1.
VEX.256.66.0F.WIG 55 /r
VANDNPD ymm1, ymm2, ymm3/m256
VEXInvalidValidValidAVXANDs packed double-precision floating-point values from the inverted form of ymm3/m256 and ymm2. Stores the result in ymm1.
EVEX.128.66.0F.W1 55 /r
VANDNPD xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst
EVEXInvalidValidValidAVX512VL
AVS512DQ
ANDs packed double-precision floating-point values from the inverted form of xmm3/m128/m64bcst and xmm2. Stores the result in xmm1.
EVEX.256.66.0F.W1 55 /r
VANDNPD ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst
EVEXInvalidValidValidAVX512VL
AVS512DQ
ANDs packed double-precision floating-point values from the inverted form of ymm3/m256/m64bcst and ymm2. Stores the result in ymm1.
EVEX.512.66.0F.W1 55 /r
VANDNPD zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst
EVEXInvalidValidValidAVX512DQANDs packed double-precision floating-point values from the inverted form of zmm3/m512/m64bcst and zmm2. Stores the result in zmm1.

Encoding

EncodingTuple TypeOperand 1Operand 2Operand 3
LEGACYN/AModRM.reg[rw]ModRM.r/m[r]
VEXN/AModRM.reg[rw]VEX.vvvv[r]ModRM.r/m[r]
EVEXFullModRM.reg[rw]EVEX.vvvv[r]ModRM.r/m[r]

Description

The (V)ANDNPD instruction ANDs two, four, or eight 64 bit integer values from the inverted form of the first source operand to the second source operand. The result is stored in in the destination operand.

This instruction, despite being named as if it operates on floating-point numbers, internally operates on 64 bit integers. The "Operation" section below has been updated to reflect this (using SimdU64 instead of SimdF64).

All versions except the legacy SSE version zero the unused upper SIMD register bits.

Operation

This pseudo-code uses C# syntax. A list of the types used is available here.
public void ANDNPD(SimdU64 dest, SimdU64 src)
{
  dest[0] = ~dest[0] & src[0];
  dest[1] = ~dest[1] & src[1];
  // dest[2..Simd.Max] (unmodified)
}

void VANDNPD_Vex(SimdU64 dest, SimdU64 src1, SimdU64 src2, int kl)
{
  for (int n = 0; n < kl, n++)
    dest[n] = ~src1[n] & src2[n];
  dest[kl..Simd.MAX] = 0;
}
public void VANDNPD_Vex128(SimdU64 dest, SimdU64 src1, SimdU64 src2)
{
  VANDNPD_Vex(dest, src1, src2, 2);
}
public void VANDNPD_Vex256(SimdU64 dest, SimdU64 src1, SimdU64 src2)
{
  VANDNPD_Vex(dest, src1, src2, 4);
}

void VANDNPD_EvexMemory(SimdU64 dest, SimdU64 src1, SimdU64 src2, KMask k, int kl)
{
  for (int n = 0; n < kl, n++)
  {
    if (k[n])
    {
      if (EVEX.b)
        dest[n] = ~src1[n] & src2[0];
      else
        dest[n] = ~src1[n] & src2[n];
    }
    else if (EVEX.z)
    {
      dest[n] = 0;
    }
  }
  dest[kl..Simd.MAX] = 0;
}
public void VANDNPD_Evex128Memory(SimdU64 dest, SimdU64 src1, SimdU64 src2, KMask k)
{
  VANDNPD_EvexMemory(dest, src1, src2, k, 2);
}
public void VANDNPD_Evex256Memory(SimdU64 dest, SimdU64 src1, SimdU64 src2, KMask k)
{
  VANDNPD_EvexMemory(dest, src1, src2, k, 4);
}
public void VANDNPD_Evex512Memory(SimdU64 dest, SimdU64 src1, SimdU64 src2, KMask k)
{
  VANDNPD_EvexMemory(dest, src1, src2, k, 8);
}

void VANDNPD_EvexRegister(SimdU64 dest, SimdU64 src1, SimdU64 src2, KMask k, int kl)
{
  for (int n = 0; n < kl, n++)
  {
    if (k[n])
      dest[n] = ~src1[n] & src2[n];
    else if (EVEX.z)
      dest[n] = 0;
  }
  dest[kl..Simd.MAX] = 0;
}
public void VANDNPD_Evex128Register(SimdU64 dest, SimdU64 src1, SimdU64 src2, KMask k)
{
  VANDNPD_EvexRegister(dest, src1, src2, k, 2);
}
public void VANDNPD_Evex256Register(SimdU64 dest, SimdU64 src1, SimdU64 src2, KMask k)
{
  VANDNPD_EvexRegister(dest, src1, src2, k, 4);
}
public void VANDNPD_Evex512Register(SimdU64 dest, SimdU64 src1, SimdU64 src2, KMask k)
{
  VANDNPD_EvexRegister(dest, src1, src2, k, 8);
}

C Intrinsics

Exceptions

SIMD Floating-Point

None

Other

VEX encoded form: see Exceptions Type 4.

EVEX encoded form: see Exceptions Type E4.

Manual Changes

This is a list of changes that have been made from the Intel® 64 and IA-32 Architectures Software Developer’s Manual. These changes were against version 73 (dated ).

  • The VEX form mnemonics (VEX.###.66.0F.WIG 55 /r) are incorrectly written as VEX.###.66.0F 55 /r (no WIG)