ANDN: Logical AND NOT

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Opcode and MnemonicEncoding16 bit Mode32 bit Mode64 bit ModeCPUID Feature FlagDescription
VEX.LZ.0F38.W0 F2 /r
ANDN r32a, r32b, r/m32
VEXInvalidValidValidBMI1ANDs the inverted form of r/m32 with r32b. Stores the result in r32a.
VEX.LZ.0F38.W1 F2 /r
ANDN r64a, r64b, r/m64
VEXInvalidInvalidValidBMI1ANDs the inverted form of r/m64 with r64b. Stores the result in r64a.

Encoding

EncodingOperand 1Operand 2
VEXModRM.reg[w]VEX.vvvv[r]ModRM.r/m[r]

Description

The ANDN instruction performs a logical AND against the inverted form of the first source operand with the unchanged second source operand. The result is stored in in the destination operand.

The operand size (W bit) is always 32 bits if not in Long Mode. In other words, in Protected and Compatibility Mode, VEX.W1 is treated as VEX.W0.

The length field (L bit) must be zero (signifying 128 bit vectors). Attempts to execute with VEX.L1 (256 bit vectors) will cause a #UD exception.

Operation

This pseudo-code uses C# syntax. A list of the types used is available here.
public void ANDN_32(ref uint dest, uint src1, uint src2)
{
  dest = ~src1 & src2;
}

public void ANDN_64(ref ulong dest, ulong src1, ulong src2)
{
  dest = ~src1 & src2;
}

Flags Affected

CF (carry flag)
Cleared.
PF (parity flag)
Undefined.
AF (auxiliary flag)
Undefined.
ZF (zero flag)
Set according to the result.
SF (sign flag)
Set according to the result.
OF (overflow flag)
Cleared.

Exceptions

SIMD Floating-Point

None

Other

See Exceptions Type 13.

#UD
If VEX.L is not 0.

Manual Changes

This is a list of changes that have been made from the Intel® 64 and IA-32 Architectures Software Developer’s Manual. These changes were against version 73 (dated ).

  • The ANDN r64a, r64b, r/m64 form is incorrectly documented as being "not encodable" in 32 bit mode. This is misleading as it is encodable, but is defined to be treated as the 32 bit form.
  • The #UD exception is not present in their exceptions list.