AND: Logical AND

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Opcode and MnemonicEncoding16 bit Mode32 bit Mode64 bit ModeDescription
24 ib
AND AL, imm8
AIValidValidValidANDs imm8 into AL.
25 iw
AND AX, imm16
AIValidValidValidANDs imm16 into AX.
25 id
AND EAX, imm32
AIValidValidValidANDs imm32 into EAX.
REX.W 25 id
AND RAX, imm32
AINot EncodableNot EncodableValidANDs imm32 (sign extended to 64 bits) into RAX.
80 /r ib
AND r/m8, imm8
MIValidValidValidANDs imm8 into r/m8.
REX 80 /r ib
AND r/m8*, imm8
MINot EncodableNot EncodableValidANDs imm8 into r/m8.
81 /4 iw
AND r/m16, imm16
MIValidValidValidANDs imm16 into r/m16.
81 /4 id
AND r/m32, imm32
MIValidValidValidANDs imm32 into r/m32.
REX.W 81 /r id
AND r/m64, imm32
MINot EncodableNot EncodableValidANDs imm32 (sign extended to 64 bits) into r/m64.
82 /4 ib
AND r/m8, imm8
MIValidValidInvalidUndocumented alias for 80 /4 ib. ANDs imm8 (sign extended to 8 bits) into r/m8.
83 /4 ib
AND r/m16, imm8
MIValidValidValidANDs imm8 (sign extended to 16 bits) into r/m16.
83 /4 ib
AND r/m32, imm8
MIValidValidValidANDs imm8 (sign extended to 32 bits) into r/m32.
REX.W 83 /4 ib
AND r/m64, imm8
MINot EncodableNot EncodableValidANDs imm8 (sign extended to 64 bits) into r/m64.
20 /r
AND r/m8, r8
MRValidValidValidANDs r8 into r/m8.
REX 20 /r
AND r/m8*, r8
MRNot EncodableNot EncodableValidANDs r8 into r/m8.
21 /r
AND r/m16, r16
MRValidValidValidANDs r16 into r/m16.
21 /r
AND r/m32, r32
MRValidValidValidANDs r32 into r/m32.
REX.W 21 /r
AND r/m64, r64
MRNot EncodableNot EncodableValidANDs r64 into r/m64.
22 /r
AND r8, r/m8
RMValidValidValidANDs r/m8 into r8.
REX 22 /r
AND r8*, r/m8*
RMNot EncodableNot EncodableValidANDs r/m8 into r8.
23 /r
AND r16, r/m16
RMValidValidValidANDs r/m16 into r16.
23 /r
AND r32, r/m32
RMValidValidValidANDs r/m32 into r32.
REX.W 23 /r
AND r64, r/m64
RMNot EncodableNot EncodableValidANDs r/m64 into r64.

Encoding

EncodingOperand 1Operand 2
AIAL/AX/EAX/RAX[rw]imm8/16/32[r]
MIModRM.r/m[rw]imm8/16/32[r]
MRModRM.r/m[rw]ModRM.reg[r]
RMModRM.reg[rw]ModRM.r/m[r]

Description

The AND instruction performs a logical AND with the destination operand against the source operand and stores the result in the destination operand. The result is stored in in the destination operand.

This instruction can be used with the LOCK prefix to allow atomic execution.

In 64 bit mode, the default operand size is 32 bits, but REX.W will change it to 64 bits.

Operation

This pseudo-code uses C# syntax. A list of the types used is available here.
// `src` is sign extended to the width of `dest`

public void AND_8(ref byte dest, byte src)
{
  dest = dest & src;
}

public void AND_16(ref ushort dest, ushort src)
{
  dest = dest & src;
}

public void AND_32(ref uint dest, uint src)
{
  dest = dest & src;
}

public void AND_64(ref ulong dest, ulong src)
{
  dest = dest & src;
}

Flags Affected

CF (carry flag)
Cleared.
PF (parity flag)
Set according to the result.
AF (auxiliary flag)
Undefined.
ZF (zero flag)
Set according to the result.
SF (sign flag)
Set according to the result.
OF (overflow flag)
Cleared.

Exceptions

Protected Mode

#GP(0)
If the destination is located in a non-writable segment.
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#UD
If the LOCK prefix is used but the destination is not a memory operand.

Real-Address Mode

#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
#UD
If the LOCK prefix is used but the destination is not a memory operand.

Virtual-8086 Mode

#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
#UD
If the LOCK prefix is used but the destination is not a memory operand.

Compatibility Mode

Same exceptions as in protected mode.

Long Mode

#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If a memory operand address is in a non-canonical form.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
#UD
If the LOCK prefix is used but the destination is not a memory operand.

Manual Changes

This is a list of changes that have been made from the Intel® 64 and IA-32 Architectures Software Developer’s Manual. These changes were against version 73 (dated ).

  • REX 20 /r is incorrectly described as "r/m64 AND r8 (sign-extended)."
  • REX 22 /r is incorrectly described as "r/m64 AND r8 (sign-extended)."