ADDSUBPD: Add/Subtract Packed Double-Precision Floating-Point Values

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Opcode and MnemonicEncoding16 bit Mode32 bit Mode64 bit ModeCPUID Feature FlagDescription
66 0F D0 /r
ADDSUBPD xmm1, xmm2/m128
LEGACYInvalidValidValidSSE3Add/subtract packed double-precision floating point values from xmm2/m128 and xmm1. Stores the result in xmm1.
VEX.128.66.0F.WIG D0 /r
VADDSUBPD xmm1, xmm2, xmm3/m128
VEXInvalidValidValidAVXAdd/subtract packed double-precision floating point values from xmm3/m128 and xmm2. Stores the result in xmm1.
VEX.256.66.0F.WIG D0 /r
VADDSUBPD ymm1, ymm2, ymm3/m256
VEXInvalidValidValidAVXAdd/subtract packed double-precision floating point values from ymm2/m256 and ymm2. Stores the result in ymm1.

Encoding

EncodingOperand 1Operand 2Operand 3
LEGACYModRM.reg[rw]ModRM.r/m[r]
VEXModRM.reg[w]VEX.vvvv[r]ModRM.r/m[r]

Description

The (V)ADDSUBPD instruction performs two operations: It subtracts the odd numbered double-precision floating-point values, and adds the even numbered ones. These operations are done as src1 op src2 (where op is either addition or subtraction). The result is stored in in the destination operand.

All versions except the legacy SSE version zero the unused upper SIMD register bits.

Operation

This pseudo-code uses C# syntax. A list of the types used is available here.
public void ADDSUBPD(SimdF64 dest, SimdF64 src)
{
  dest[0] -= src[0];
  dest[1] += src[1];
  // dest[2..Simd.Max] (unmodified)
}

public void VADDSUBPD_Vex128(SimdF64 dest, SimdF64 src1, SimdF64 src2)
{
  dest[0] -= src[0];
  dest[1] += src[1];
  dest[2..Simd.Max] = 0;
}
public void VADDSUBPD_Vex256(SimdF64 dest, SimdF64 src1, SimdF64 src2)
{
  dest[0] -= src[0];
  dest[1] += src[1];
  dest[2] -= src[2];
  dest[3] += src[3];
  dest[4..Simd.Max] = 0; // see note 1
}

Notes

  1. The manual makes no mention of if this instruction form clears the upper bits or not. It is assumed that it would.

C Intrinsics

Exceptions

SIMD Floating-Point

Overflow, Underflow, Invalid, Precision, Denormal

Other

See Exceptions Type 2.