ADDSS: Add Scalar Single-Precision Floating-Point Value

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Opcode and MnemonicEncoding16 bit Mode32 bit Mode64 bit ModeCPUID Feature FlagDescription
F3 0F 58 /r
ADDSS xmm1, xmm2/m32
LEGACYInvalidValidValidSSE2Adds a single single-precision floating-point value from xmm2/m32 and xmm1. Stores the result in xmm1.
VEX.LIG.F3.0F.WIG 58 /r
VADDSS xmm1, xmm2, xmm3/m32
VEXInvalidValidValidAVXAdds a single single-precision floating-point value from xmm3/m32 and xmm2. Stores the result in xmm1.
EVEX.LIG.F3.0F.W0 58 /r
VADDSS xmm1 {k1}{z}, xmm2, xmm3/m32 {er}
EVEXInvalidValidValidAVX512FAdds a single single-precision floating-point value from xmm3/m32 and xmm2. Stores the result in xmm1 using writemask k1.

Encoding

EncodingTuple TypeOperand 1Operand 2Operand 3
LEGACYN/AModRM.reg[rw]ModRM.r/m[r]
VEXN/AModRM.reg[w]VEX.vvvv[r]ModRM.r/m[r]
EVEXTuple1 ScalarModRM.reg[w]EVEX.vvvv[r]ModRM.r/m[r]

Description

The (V)ADDSS instruction adds a single single-precision floating-point from the first source operand and the second source operand. The result is stored in in the destination operand.

The legacy SSE version (ADDSS) works on the lowest 32 bits and leaves all others unchanged.

The AVX versions (VADDSS) work on the lowest 32 bits, but also copy the next 96 bits from the first source operand to the destination. Afterwards, all unchanged bits in the destination are zeroed.

Although this instruction works with (E)VEX.LIG, Intel recommends that assemblers set (E)VEX.L to 0. Encoding with (E)VEX.L being 1 may not be allowed in the future.

Operation

This pseudo-code uses C# syntax. A list of the types used is available here.
public void ADDSS(SimdF32 dest, SimdF32 src)
{
  dest[0] += src[0];
  // dest[1..Simd.MAX] (unchanged)
}

public void VADDSS_Vex(SimdF32 dest, SimdF32 src1, SimdF32 src2)
{
  dest[0] = src1[0] + src2[0];
  dest[1] = src1[1];
  dest[2] = src1[2];
  dest[3] = src1[3];
  dest[4..Simd.MAX] = 0;
}

public void VADDSS_EvexMemory(SimdF32 dest, SimdF32 src1, SimdF32 src2, KMask k)
{
  if (k[0])
    dest[0] = src1[0] + src2[0];
  else if (EVEX.z)
    dest[0] = 0;
  dest[1] = src1[1];
  dest[2] = src1[2];
  dest[3] = src1[3];
  dest[4..Simd.MAX] = 0;
}

public void VADDSS_EvexRegister(SimdF32 dest, SimdF32 src1, SimdF32 src2, KMask k)
{
  if (EVEX.b)
    SetRoundingForThisInstruction(EVEX.rc);
  else
    SetRoundingForThisInstruction(MXCSR.rc);

  if (k[0])
    dest[0] = src1[0] + src2[0];
  else if (EVEX.z)
    dest[0] = 0;
  dest[1] = src1[1];
  dest[2] = src1[2];
  dest[3] = src1[3];
  dest[4..Simd.MAX] = 0;
}

C Intrinsics

Exceptions

SIMD Floating-Point

Overflow, Underflow, Invalid, Precision, Denormal

Other

VEX encoded form: see Exceptions Type 2.

EVEX encoded form: see Exceptions Type E2.