ADDPS: Add Packed Single-Precision Floating-Point Values

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Opcode and MnemonicEncoding16 bit Mode32 bit Mode64 bit ModeCPUID Feature FlagDescription
NP 0F 58 /r
ADDPS xmm1, xmm2/m128
LEGACYInvalidValidValidSSEAdds packed single-precision floating-point values from xmm2/m128 and xmm1. Stores the result in xmm1.
VEX.128.0F.WIG 58 /r
VADDPS xmm1, xmm2, xmm3/m128
VEXInvalidValidValidAVXAdds packed single-precision floating-point values from xmm3/m128 and xmm2. Stores the result in xmm1.
VEX.256.0F.WIG 58 /r
VADDPS ymm1, ymm2, ymm3/m256
VEXInvalidValidValidAVXAdds packed single-precision floating-point values from ymm3/m256 and ymm2. Stores the result in ymm1.
EVEX.128.0F.W0 58 /r
VADDPS xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst
EVEXInvalidValidValidAVX512VL
AVX512F
Adds packed single-precision floating-point values from xmm3/m128/m32bcst and xmm2. Stores the result in xmm1 using writemask k1.
EVEX.256.0F.W0 58 /r
VADDPS ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst
EVEXInvalidValidValidAVX512VL
AVX512F
Adds packed single-precision floating-point values from ymm3/m256/m32bcst and ymm2. Stores the result in ymm1 using writemask k1.
EVEX.512.0F.W0 58 /r
VADDPS zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst {er}
EVEXInvalidValidValidAVX512FAdds packed single-precision floating-point values from zmm3/m512/m32bcst and zmm2. Stores the result in zmm1 using writemask k1.

Encoding

EncodingTuple TypeOperand 1Operand 2Operand 3
LEGACYN/AModRM.reg[rw]ModRM.r/m[r]
VEXN/AModRM.reg[w]VEX.vvvv[r]ModRM.r/m[r]
EVEXFullModRM.reg[w]EVEX.vvvv[r]ModRM.r/m[r]

Description

The (V)ADDPS instruction adds four, eight, or sixteen single-precision floating-point values from the first source operand to the second source operand. The result is stored in in the destination operand.

All versions except the legacy SSE version zero the unused upper SIMD register bits.

Operation

This pseudo-code uses C# syntax. A list of the types used is available here.
public void ADDPS(SimdF32 dest, SimdF32 src)
{
  dest[0] += src[0];
  dest[1] += src[1];
  dest[2] += src[2];
  dest[3] += src[3];
  // dest[4..Simd.Max] (unmodified)
}

void VADDPS_Vex(SimdF32 dest, SimdF32 src1, SimdF32 src2, int kl)
{
  for (int n = 0; n < kl, n++)
    dest[n] = src1[n] + src2[n];
  dest[kl..Simd.MAX] = 0;
}
public void VADDPS_Vex128(SimdF32 dest, SimdF32 src1, SimdF32 src2)
{
  VADDPS_Vex(dest, src1, src2, 4);
}
public void VADDPS_Vex256(SimdF32 dest, SimdF32 src1, SimdF32 src2)
{
  VADDPS_Vex(dest, src1, src2, 8);
}

void VADDPS_EvexMemory(SimdF32 dest, SimdF32 src1, SimdF32 src2, KMask k, int kl)
{
  for (int n = 0; n < kl, n++)
  {
    if (k[n])
    {
      if (EVEX.b)
        dest[n] = src1[n] + src2[0];
      else
        dest[n] = src1[n] + src2[n];
    }
    else if (EVEX.z)
    {
      dest[n] = 0;
    }
  }
  dest[kl..Simd.MAX] = 0;
}
public void VADDPS_Evex128Memory(SimdF32 dest, SimdF32 src1, SimdF32 src2, KMask k)
{
  VADDPS_EvexMemory(dest, src1, src2, k, 4);
}
public void VADDPS_Evex256Memory(SimdF32 dest, SimdF32 src1, SimdF32 src2, KMask k)
{
  VADDPS_EvexMemory(dest, src1, src2, k, 8);
}
public void VADDPS_Evex512Memory(SimdF32 dest, SimdF32 src1, SimdF32 src2, KMask k)
{
  VADDPS_EvexMemory(dest, src1, src2, k, 16);
}

void VADDPS_EvexRegister(SimdF32 dest, SimdF32 src1, SimdF32 src2, KMask k, int kl)
{
  if (kl == 8 && EVEX.b)
    SetRoundingForThisInstruction(EVEX.rc);
  else
    SetRoundingForThisInstruction(MXCSR.rc);

  for (int n = 0; n < kl, n++)
  {
    if (k[n])
      dest[n] = src1[n] + src2[n];
    else if (EVEX.z)
      dest[n] = 0;
  }
  dest[kl..Simd.MAX] = 0;
}
public void VADDPS_Evex128Register(SimdF32 dest, SimdF32 src1, SimdF32 src2, KMask k)
{
  VADDPS_EvexRegister(dest, src1, src2, k, 4);
}
public void VADDPS_Evex256Register(SimdF32 dest, SimdF32 src1, SimdF32 src2, KMask k)
{
  VADDPS_EvexRegister(dest, src1, src2, k, 8);
}
public void VADDPS_Evex512Register(SimdF32 dest, SimdF32 src1, SimdF32 src2, KMask k)
{
  VADDPS_EvexRegister(dest, src1, src2, k, 16);
}

C Intrinsics

Exceptions

SIMD Floating-Point

Overflow, Underflow, Invalid, Precision, Denormal

Other

VEX encoded form: see Exceptions Type 2.

EVEX encoded form: see Exceptions Type E2.